Research interests

• technical diagnostics;
• genetic algorithms;
• genetic programming;
• application of the genetic algorithms in technical diagnostics.

Diplomas

• 2008 - Certificate of Competition, Intel® Software College, "Multi-core programming for Academia , Multi-core Technological School", Kharkiv, May 2007;
• 2004 - Associated Professor diploma in Automated Control System department, Donetsk National Technical University;
• 2000 - PhD diploma in "Computers, systems & nets", Donetsk National Technical University;
• 1995 - Specialist diploma in "Mathematics", Donetsk State University.

Career

• 2005- present time - senior scientific researcher in Theory Control System Department, Institute of Applied Mathematics & Mechanics;
• 2002- 2005 - scientific researcher in Theory Control System Department, Institute of Applied Mathematics & Mechanics;
• 2001-2002 - junior scientific researcher in Theory Control System Department, Institute of Applied Mathematics & Mechanics;
• 1998-2001 - engineer in Theory Control System Department, Institute of Applied Mathematics & Mechanics;
• 1995-1998 - PhD student in Institute of Applied Mathematics & Mechanics.

Part time:

• 2007 - present time - head of State Qualification Committee,Donetsk University of Artificial Intelligence;
• 2005 - present time - head of State Qualification Committee, Donetsk National Technical University;
• 2001 - present time - member of State Qualification Committee in Donetsk College of Industrial Automation;
• 2000 - present time - associated professor in Automated Control System department, Donetsk National Technical University.

 

Download full publications list

Publications

1. Scalable parallel genetic algorithm for identifying sequences construction
    
   The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads. Each thread evaluates fitness-function for own individual by simulating circuit’s behavior. This schema is known as «master-slave».  We also study the scalability of this type parallel GA on systems with large numbers of computational cores. We present results for circuits in the ISCAS-89 benchmark set obtained on the Intel’s MTL with 12 cores.
    
   Download in PDF format
2. Parallel fault simulation algorithm for multi-core systems with common memory / Electronic Modeling.- 2011.- V.33, №2.- P.93-106.
    
   Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.
   
    
   Download in PDF format
3. Adaptation of parallel genetic algorithms of the identifying sequences generation for multi-core systems (in print)
    
   The article offers a practical approach to the adaptation of parallel genetic algorithms for workstations with multi-core processors. The main idea is to parallelize the procedures for simulation of digital circuits, that serve as a base for evaluating of the quality of constructed sequences. Software implementation is based on multi-threaded programming. The experimental results on ISCAS-89 circuits are reported.
4. Y.A. Skobtsov, D.E. Ivanov, V.Y. Skobtsov Evolutionary distributed test generation methods for digital circuits // Proc. of 8th International Workshop on Boolean Problems, September 18-19, 2008, Freiberg, Germany.- pp.213-218.
    
    
   Download in PDF format
5. Skobtsov Y.A., El-Khatib, Ivanov D.E. Distributed Genetic Algorithm of Test Generation For Digital Circuits // Proceedings of the 10th Biennial Baltic Electronics Conference.-Tallinn Technical University,2006.-p.281-284.
    
   Abstract  – The distributed genetic algorithms are considered for problem of test generation. The different forms of parallelization of genetic algorithms  are investigated for test generation.
   Keywords – genenic algorithms, distributed calculations, test generation, fault simulation, digital circuits.
   
    
   Download in PDF format
6. D.E. Ivanov Parallel fault simulation on multi-core processors // «Радіоелектронні і комп’ютерні системи», 2009.- №6(40).- С.109-112.
    
   In this paper we propose a fault simulation algorithm that utilizes all cores in multi-core processors. We adapt for multi-core workstation our early proposed distributed fault simulation algorithm. Proposed algorithm uses multi thread execution. The algorithm is based on the well-known «master-slave» approach in which one thread is nominated as a master and controls the calculation on all the other cores of processor. To maximize utilization of the cores a scheme with static fault list partitioning is used. The speed-up coefficient of the simulation time obtained during machine experiments is up to 3.44 times on the quad core system.
    
   Download in PDF format
7. Skobtsov Y.A., El-Khatib, Ivanov D.E. Distributed Fault Simulation and Genetic Test Generation of Digital Circuits // Proceedings of IEEE East-West Design&Test Workshop (EWDT’06).- 2006: Sochi.- p.89-94.
    
   Fault simulation is on of the most highly compute-intensive task in the technical diagnostics. One of the ways to speed-up this process is a parallelization on the calculation cluster. In this paper a distributed algorithm for fault simulation of digital circuits is presented. It is based on the well-known «master-slave» approach in which one processor is nominating as a master and rules all calculation on the all slave’s processors. To reach the maximal utilization of the processors in the cluster it is used schema with static fault list partitioning.
   
    
   Download in PDF format
8. Д.Е. Иванов, Ю.А. Скобцов, Эль-Хатиб А.И. Распределённое параллельное моделирование цифровых схем с неисправностями // Наукові праці Донецького національного технічного університету. Серія: “Обчислювальна техніка та автоматизація”. Випуск 107.-Донецьк: ДонНТУ. – 2006.- С.128-134.
    
   Fault simulation is on of the most highly compute-intensive task in the technical diagnostics. One of the ways to speed-up this process is a parallelization on the calculation cluster. In this paper a distributed algorithm for fault simulation of digital circuits is presented. It is based on the well-known «master-slave» approach in which one processor is nominating as a master and rules all calculation on the all slave’s processors. To reach the maximal utilization of the processors in the cluster it is used schema with static fault list partitioning.
    
   Download in PDF format
9. Иванов Д.Е. Генетический алгоритм оптимизации рассеивания тепловой энергии входных тестовых последовательностей // Наукові праці Донецького національного технічного університету. Серія: “Обчислювальна техніка та автоматизація”.
    
   In this paper a new approach for solving the problem of the optimization of the power dissipation under test sequence application is proposed. This approach is based on the redundancy of the test sequences and consists of the steps: redundant test generation, evaluating power dissipation for generated test sequences and construction of the subset of sequences with optimal parameters. The last stage is based on the genetic algorithm. Also we give the results of the computer experiments on the ISCAS-89 benchmark circuits that show the effectiveness of the proposed approach.
   
    
   Download in PDF format
10. Д.Е. Иванов, Ю.А. Скобцов, А.И. Эль-Хатиб Построение инициализирующих последовательностей синхронных цифровых схем с помощью генетических алгоритмов.- Проблеми інформаційних технологій.-2007.-№1.-с.158-164.
     
    В настоящее время для решения многих «классических» задач технической диагностики применяются нетрадиционные подходы, в частности - генетические алгоритмы. Одной из таких задач является построение инициализирующих последовательностей для синхронных последовательностных схем. В статье предлагается генетический алгоритм построения таких последовательностей. В данном алгоритме вычисление оценочной функции основано на моделировании работы исправной схемы. Для программы, реализующей предложенный алгоритм, приведены результаты проведённых машинных экспериментов для схем из международного каталога ISCAS-89.
     
    Download in PDF format
11. Иванов Д.Е. Генетические алгоритмы построения идентифицирующих последовательностей для цифровых схем с памятью // Наукові праці Донецького національного технічного університету. Серія: “Обчислювальна техніка та автоматизація”. Випуск 14(129).-Донецьк: ДонНТУ. – 2008.- С.97-106.
     
    In the life cycle of development of digital circuits developer need to solve the several problems of building of input sequences: test, initializing and verifying of equivalence. In this paper a generalized approach to solving this problem is presented. It based on the genetic algorithm and avoids some problems that are intrinsic to the traditional deterministic methods.
     
    Download in PDF format
12. Иванов Д.Е., Чебанов П.А. Взаимодействие компонент в распределённых генетических алгоритмах генерации тестов // Наукові праці Донецького національного технічного університету. Серія: “Обчислювальна техніка та автоматизація”. Випуск 16(147).-Донецьк: ДонНТУ, 2009.- С.121-127.
     
    In this paper the problem of construction of the distributed genetic algorithms that based on the «islands» model is discussed. In this model one calculation system is nominated as server and manage the interaction among the clients. Direct search of the problem solution is performed on the clients’ machines. The algorithm of the work of the server and clients are considered in detail. Also we propose the schema of the synchronous interaction between the main server and «islands».
     
    Download in PDF format
13. Лекції за курсом «Моделювання» для студентів напрямку підготовки «Комп’ютерні науки» та «Комп’ютерна інженерія» / Укладач: Іванов Д.Є. – Донецьк: ДонНТУ, 2009,- 59с.
     
    Курс лекцій присвячено питанням математичного моделювання роботи обчислювальних систем. Зокрема розглянуті питання побудови математичних моделей ОС, аналізу та синтезу цифрових керуючих систем. Освічені питання математичного аналізу систем масового обслуговування та їх застосування до задач синтезу систем оперативної обробки. Докладно викладаються питання планування робіт в ОС. Наведені питання, які пропонуються під час проведення модульних контролів.
    Курс лекцій призначено для студентів напрямку підготовки 6.050101 «Комп’ютерні науки» та 6.050102 «Комп’ютерна інженерія» при вивченні курсу «Моделювання».